An LDMOS device is basically a metal oxide semiconductor field effect transistor (MOSFET) fabricated using a double-diffusion process with coplanar drain and source regions. A prior art LDMOS device 100 is shown in a cross-sectional view in FIG. 1. An N+ buried layer 104 of silicon is formed within the top portion of a P-substrate 102. A high voltage P well (HVPW) 108 extends downwardly from the top surface of the substrate 102. The HVPW 108 includes an N+ source 110 having a distance L from the junction between an adjacent high voltage N well (HVNW) 106 and the N+ source 110, wherein distance L defines the channel of the device 100. A gate 112 is formed proximate the source 110 over a field oxide (FOX). The LDMOS device 100 includes a drain 114 comprising an N+ material formed in the HVNW 106, as shown. Applying a positive voltage to the gate 112 induces a current to flow through the channel from the N+ source 110 into the HVNW 106 to be collected at the N+ drain 114.
A problem with the prior art LDMOS device 100 shown in FIG. 1 is that if the LDMOS device 100 is connected to an inductor load, such as to drive a digital versatile disc (DVD), a transient negative voltage may be fed back at the drain 114 when the power is off. The transient negative voltage can create leakage current. The leakage current results from a forward bias voltage in the PN diode creating leakage current from the drain 114 to the substrate 102, as shown in FIG. 1 at IL.
A schematic diagram 120 of a model of this leakage current IL phenomenon is shown in FIG. 2. In the schematic 120, the voltage V represents a voltage across drain 114 to P-substrate 102, resistor R represents the resistance between the drain 114 and the P-Substrate 102, and the inductor L represents an inductor load. At time=t0, when power is turned off of the device 100, effectively, switch S is switched, causing the leakage current IL to flow from the drain 114 to the substrate 102. This leakage IL degrades device performance, causing a latch-up effect, early breakdown, and reliability issues for the LDMOS device 100, as examples.
A chart showing the voltage VL, which creates the leakage current IL discussed herein with reference to FIGS. 1 and 2 is shown at 122 in FIG. 3. For example, a positive voltage exists at the drain when the LDMOS device 100 is turned on, e.g., when a positive voltage V is applied to the gate 112. A negative voltage spike −V is produced at time t=t1 when the power is turned off of the device 100, e.g., when the positive voltage V is removed from the gate 112.
What is needed in the art is a LDMOS device and method of manufacturing thereof that does not have the drain 114 to substrate 102 leakage current problems experienced in prior art LDMOS devices 100.